In memories, a continuing desire is increased speed, which primarily is limited by the read operation in which sensing of the logic state of memory cells is performed. Typical issues are amplification and timing. It is important to only begin sensing when the signal being sensed is sufficiently developed. But due to difficulties in manufacturing in providing perfectly matched transistors, amplification of the signal can begin in the wrong direction early in the signal development stage. Any waiting for signal development adds to the read time, which is undesirable. This tension between waiting to ensure sufficient signal development and early sensing for fast read times is generally present in the design of a memory. Thus, any improvements in the ability to begin the sensing as early as possible while avoiding beginning sensing when the signal being sensed is not sufficiently developed is desirable.